library ieee;
use IEEE.numeric_std.all;
use ieee.std_logic_1164.all;

entity DecIncCounter is 
	port (
	clk							: in std_logic;
	dec, inc					: in std_logic;
	count						: out unsigned(2 downto 0)
	);
end entity;

Architecture rtl of DecIncCounter is
	signal nextCount			: unsigned(2 downto 0);
	signal div_clk				: std_logic;
	signal div_cnt				: integer range 0 to 7;
begin
	process(clk)
	begin
		if(rising_edge(clk)) then
			div_cnt <= div_cnt + 1;
			if(div_cnt < 4) then
				div_clk <= '0';
			else
				div_clk <= '1';
			end if;
		end if;
	end process;
	
	
	process(div_clk)
	begin
		if(div_clk = '1' and div_clk'event) then
			if(dec = '1' xor inc = '1') then
				if(dec = '1') then
					if(nextCount - 1 >= 0) then
						nextCount <= nextCount - 1;
					else
						nextCount <= "000";
					end if;
				elsif (inc = '1') then
					if (nextCount + 1 <= 7) then
						nextCount <= nextCount + 1;
					else
						nextCount <= "000";
					end if;
				end if;
			end if;
		end if;
	end process;
	count <= nextCount;
end rtl;
